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-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 13.4
--  \   \         Application : sch2hdl
--  /   /         Filename : top1.vhf
-- /___/   /\     Timestamp : 11/23/2017 19:26:31
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: sch2hdl -intstyle ise -family spartan3a -flat -suppress -vhdl F:/miaobiao/top1.vhf -w F:/miaobiao/top1.sch
--Design Name: top1
--Device: spartan3a
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesized and simulated, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity top_MUSER_top1 is
   port ( carryin  : in    std_logic; 
          clk      : in    std_logic; 
          reset    : in    std_logic; 
          carryout : out   std_logic; 
          h1       : out   std_logic_vector (3 downto 0); 
          h10      : out   std_logic_vector (3 downto 0); 
          m1       : out   std_logic_vector (3 downto 0); 
          m10      : out   std_logic_vector (3 downto 0); 
          s1       : out   std_logic_vector (3 downto 0); 
          s10      : out   std_logic_vector (3 downto 0));
end top_MUSER_top1;

architecture BEHAVIORAL of top_MUSER_top1 is
   signal XLXN_2   : std_logic;
   signal XLXN_9   : std_logic;
   signal XLXN_16  : std_logic;
   signal XLXN_22  : std_logic;
   signal XLXN_31  : std_logic;
   component counter6
      port ( clk      : in    std_logic; 
             carryin  : in    std_logic; 
             reset    : in    std_logic; 
             carryout : out   std_logic; 
             timeout  : out   std_logic_vector (3 downto 0));
   end component;
   
   component counter10
      port ( clk      : in    std_logic; 
             carryin  : in    std_logic; 
             reset    : in    std_logic; 
             carryout : out   std_logic; 
             timeout  : out   std_logic_vector (3 downto 0));
   end component;
   
begin
   XLXI_1 : counter6
      port map (carryin=>XLXN_2,
                clk=>clk,
                reset=>reset,
                carryout=>carryout,
                timeout(3 downto 0)=>h10(3 downto 0));
   
   XLXI_2 : counter10
      port map (carryin=>XLXN_31,
                clk=>clk,
                reset=>reset,
                carryout=>XLXN_2,
                timeout(3 downto 0)=>h1(3 downto 0));
   
   XLXI_3 : counter10
      port map (carryin=>XLXN_9,
                clk=>clk,
                reset=>reset,
                carryout=>XLXN_22,
                timeout(3 downto 0)=>s10(3 downto 0));
   
   XLXI_4 : counter10
      port map (carryin=>carryin,
                clk=>clk,
                reset=>reset,
                carryout=>XLXN_9,
                timeout(3 downto 0)=>s1(3 downto 0));
   
   XLXI_5 : counter10
      port map (carryin=>XLXN_22,
                clk=>clk,
                reset=>reset,
                carryout=>XLXN_16,
                timeout(3 downto 0)=>m1(3 downto 0));
   
   XLXI_6 : counter6
      port map (carryin=>XLXN_16,
                clk=>clk,
                reset=>reset,
                carryout=>XLXN_31,
                timeout(3 downto 0)=>m10(3 downto 0));
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity top1 is
   port ( bs    : in    std_logic; 
          clk   : in    std_logic; 
          latch : in    std_logic; 
          reset : in    std_logic; 
          seg   : out   std_logic_vector (6 downto 0); 
          sel   : out   std_logic_vector (7 downto 0));
end top1;

architecture BEHAVIORAL of top1 is
   signal XLXN_12 : std_logic;
   signal XLXN_19 : std_logic;
   signal XLXN_20 : std_logic_vector (3 downto 0);
   signal XLXN_21 : std_logic_vector (3 downto 0);
   signal XLXN_22 : std_logic_vector (3 downto 0);
   signal XLXN_23 : std_logic_vector (3 downto 0);
   signal XLXN_24 : std_logic_vector (3 downto 0);
   signal XLXN_25 : std_logic_vector (3 downto 0);
   signal XLXN_34 : std_logic_vector (3 downto 0);
   signal XLXN_35 : std_logic_vector (3 downto 0);
   signal XLXN_36 : std_logic_vector (3 downto 0);
   signal XLXN_37 : std_logic_vector (3 downto 0);
   signal XLXN_38 : std_logic_vector (3 downto 0);
   signal XLXN_39 : std_logic_vector (3 downto 0);
   signal XLXN_40 : std_logic;
   signal XLXN_41 : std_logic;
   signal XLXN_80 : std_logic;
   component top_MUSER_top1
      port ( clk      : in    std_logic; 
             reset    : in    std_logic; 
             carryin  : in    std_logic; 
             h10      : out   std_logic_vector (3 downto 0); 
             carryout : out   std_logic; 
             h1       : out   std_logic_vector (3 downto 0); 
             m10      : out   std_logic_vector (3 downto 0); 
             m1       : out   std_logic_vector (3 downto 0); 
             s1       : out   std_logic_vector (3 downto 0); 
             s10      : out   std_logic_vector (3 downto 0));
   end component;
   
   component save
      port ( key : in    std_logic; 
             clr : in    std_logic; 
             hi1 : in    std_logic_vector (3 downto 0); 
             hi0 : in    std_logic_vector (3 downto 0); 
             mi1 : in    std_logic_vector (3 downto 0); 
             mi0 : in    std_logic_vector (3 downto 0); 
             si1 : in    std_logic_vector (3 downto 0); 
             si0 : in    std_logic_vector (3 downto 0); 
             ho1 : out   std_logic_vector (3 downto 0); 
             ho0 : out   std_logic_vector (3 downto 0); 
             mo1 : out   std_logic_vector (3 downto 0); 
             mo0 : out   std_logic_vector (3 downto 0); 
             so1 : out   std_logic_vector (3 downto 0); 
             so0 : out   std_logic_vector (3 downto 0));
   end component;
   
   component fdiv100hz
      port ( clk  : in    std_logic; 
             clko : out   std_logic);
   end component;
   
   component bscontrol
      port ( key    : in    std_logic; 
             enable : out   std_logic);
   end component;
   
   component ajxd
      port ( clk  : in    std_logic; 
             keyi : in    std_logic; 
             keyo : out   std_logic);
   end component;
   
   component xianshi
      port ( clk : in    std_logic; 
             h1  : in    std_logic_vector (3 downto 0); 
             h0  : in    std_logic_vector (3 downto 0); 
             m1  : in    std_logic_vector (3 downto 0); 
             m0  : in    std_logic_vector (3 downto 0); 
             s1  : in    std_logic_vector (3 downto 0); 
             s0  : in    std_logic_vector (3 downto 0); 
             sel : out   std_logic_vector (7 downto 0); 
             seg : out   std_logic_vector (6 downto 0));
   end component;
   
begin
   XLXI_1 : top_MUSER_top1
      port map (carryin=>XLXN_40,
                clk=>XLXN_80,
                reset=>XLXN_41,
                carryout=>open,
                h1(3 downto 0)=>XLXN_35(3 downto 0),
                h10(3 downto 0)=>XLXN_34(3 downto 0),
                m1(3 downto 0)=>XLXN_37(3 downto 0),
                m10(3 downto 0)=>XLXN_36(3 downto 0),
                s1(3 downto 0)=>XLXN_38(3 downto 0),
                s10(3 downto 0)=>XLXN_39(3 downto 0));
   
   XLXI_2 : save
      port map (clr=>XLXN_41,
                hi0(3 downto 0)=>XLXN_35(3 downto 0),
                hi1(3 downto 0)=>XLXN_34(3 downto 0),
                key=>XLXN_19,
                mi0(3 downto 0)=>XLXN_37(3 downto 0),
                mi1(3 downto 0)=>XLXN_36(3 downto 0),
                si0(3 downto 0)=>XLXN_38(3 downto 0),
                si1(3 downto 0)=>XLXN_39(3 downto 0),
                ho0(3 downto 0)=>XLXN_21(3 downto 0),
                ho1(3 downto 0)=>XLXN_20(3 downto 0),
                mo0(3 downto 0)=>XLXN_23(3 downto 0),
                mo1(3 downto 0)=>XLXN_22(3 downto 0),
                so0(3 downto 0)=>XLXN_25(3 downto 0),
                so1(3 downto 0)=>XLXN_24(3 downto 0));
   
   XLXI_4 : fdiv100hz
      port map (clk=>clk,
                clko=>XLXN_80);
   
   XLXI_5 : bscontrol
      port map (key=>XLXN_12,
                enable=>XLXN_40);
   
   XLXI_6 : ajxd
      port map (clk=>XLXN_80,
                keyi=>bs,
                keyo=>XLXN_12);
   
   XLXI_7 : ajxd
      port map (clk=>XLXN_80,
                keyi=>reset,
                keyo=>XLXN_41);
   
   XLXI_8 : ajxd
      port map (clk=>XLXN_80,
                keyi=>latch,
                keyo=>XLXN_19);
   
   XLXI_9 : xianshi
      port map (clk=>clk,
                h0(3 downto 0)=>XLXN_21(3 downto 0),
                h1(3 downto 0)=>XLXN_20(3 downto 0),
                m0(3 downto 0)=>XLXN_23(3 downto 0),
                m1(3 downto 0)=>XLXN_22(3 downto 0),
                s0(3 downto 0)=>XLXN_25(3 downto 0),
                s1(3 downto 0)=>XLXN_24(3 downto 0),
                seg(6 downto 0)=>seg(6 downto 0),
                sel(7 downto 0)=>sel(7 downto 0));
   
end BEHAVIORAL;


